TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon
TECHGLAZHACKFEST 2026
07 - 08 AUGUSTNational Hackathon

Vlsi

CSE & IT — Specialized Engineering Curriculum

Course Overview

Get hands-on industrial certification in Vlsi. This curriculum is designed in alignment with corporate standards and verified internship tracks.

What You Will Learn

  • Write RTL code using Verilog HDL.
  • Understand ASIC/FPGA design flow and tools.
  • Design verification testbenches using SystemVerilog.
  • Implement Universal Verification Methodology (UVM) standards.

Course Syllabus

Interactive Roadmap Timeline

Active Stage — Weeks 1-8

Verilog HDL & Digital Design

Key Concepts & Syllabus

  • Combinational logic design
  • Sequential logic design
  • Finite State Machines (FSM)
  • ASIC design flow overview
Stage 1 of 3
Prerequisites
  • Basic Logic Gates
  • Boolean Algebra
Build Projects
  • FSM-based Traffic Light Controller
  • 16-bit RISC ALU Model in Verilog

Quick Facts

Selected Duration

12 Weeks

Schedule

Tue, Thu, Sat (10:00 AM - 12:30 PM IST)

Eligibility

Basic digital logic design understanding. Open to ECE/EE/EI graduates.

Apply For This Course

Course Instructor

Prof. Rajesh Kumar

IIT Expert

VLSI DesignFPGA Synthesis